Recessed chip IC packages are gaining acceptance in IC device interconnection technology because of efficient utilization of interconnect substrate area, low overall package profile, and reduced interconnection length. A variety of recessed chip package options are described and claimed in U.S. Pat. No. 5,608,262, issued Mar. 4, 1997 which, for purposes of this disclosure, is incorporated herein by reference.
Recessed chip packages are characterized by three components, a primary IC chip or chips, defined for the purpose of this exposition as a first level component, an intermediate interconnection substrate (IIS) which (in a conventional package) may be either an IC chip or a passive interconnection substrate, defined here as a second level component, and a system interconnection substrate (SIS) which is typically a printed circuit board (PCB) and defined as a third level component. These components are progressively larger in area so that the second level component(s) can support one or more IC chips, and the third level components can accommodate one or more second level components. In a three component package, the first level components are typically flip-chip bonded to the second level components, and the second level components are flip-bonded to the third level component, with the first level components recessed into cavities formed in the third level component.
A number of variations using this basic concept are possible, e.g. the system interconnection substrate can itself function as an intermediate interconnection substrate and attach to a fourth board level, with the second level components recessed into cavities in the fourth level component.
Recessed cavity structures have efficient interconnection arrangements, but there is an ever growing need for denser interconnections and higher interconnection performance.
In co-pending application Ser. No. 09/081,448, filed May 19, 1998, several alternative silicon-on-silicon IC package designs are described which address the problems of thermal mismatch between silicon IC chips and conventional printed wiring board materials. In common with the packages described herein, the packages in the co-pending application are also directed to interconnect arrangements using a silicon intermediate interconnection substrate. The use of silicon-on-silicon in premium interconnection assemblies is growing due in part to the nearly optimum thermomechanical design made possible by the match between the Coefficient of Thermal Expansion (CTE) of the silicon chip and the silicon interconnection substrate. In state of the art silicon-on-silicon packages, the silicon-on-silicon MCM is attached to an intermediate interconnection substrate, and the intermediate interconnection substrate is in turn mounted on a mother board. While it would seem ideal from the standpoint of thermomechanical design to construct all board levels of silicon, the size of the mother boards, and even the size of the intermediate boards, makes this option prohibitively costly. Therefore both the intermediate interconnection boards and the mother boards in multiboard assemblies are typically epoxy/glass laminates.
Typical polymer laminates are not well matched thermomechanically to the silicon-on-silicon interconnection assembly. The CTE of FR-4, the most widely used epoxy laminate printed wiring board (PWB) material, is approximately 16 ppm/.degree. C. The CTE of silicon is 2.6 ppm/.degree. C.
An approach to reducing the thermomechanical mismatch between the silicon-on-silicon assembly and the intermediate board would appear to be to construct the intermediate board of a plastic material that matches the CTE of silicon. However, the shortcoming of this approach is that the mismatch between the intermediate board and the mother board is then unacceptable.